From 3e13850ea4568176fd9ebc125089061671e30998 Mon Sep 17 00:00:00 2001 From: acass91 Date: Sat, 26 Nov 2022 01:07:29 -0700 Subject: [PATCH] verilator: add page (#9443) --- pages/common/verilator.md | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 pages/common/verilator.md diff --git a/pages/common/verilator.md b/pages/common/verilator.md new file mode 100644 index 000000000..cd7d6f260 --- /dev/null +++ b/pages/common/verilator.md @@ -0,0 +1,20 @@ +# verilator + +> Converts Verilog and SystemVerilog hardware description language (HDL) designs into a C++ or SystemC model that after compiling can be executed. +> More information: . + +- Build a specific C project in the current directory: + +`verilator --binary --build-jobs 0 -Wall {{path/to/source.v}}` + +- Create a C++ executable in a specific folder: + +`verilator --cc --exe --build --build-jobs 0 -Wall {{path/to/source.cpp}} {{path/to/output.v}}` + +- Perform linting over a code in the current directory: + +`verilator --lint-only -Wall` + +- Create XML output about the design (files, modules, instance hierarchy, logic and data types) to feed into other tools: + +`verilator --xml-output -Wall {{path/to/output.xml}}`