From 9272721e5af05373860fe90ff39cd977e0946893 Mon Sep 17 00:00:00 2001 From: "K.B.Dharun Krishna" Date: Tue, 29 Nov 2022 00:06:58 +0530 Subject: [PATCH] verilator: fix typo (#9559) --- pages/common/verilator.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pages/common/verilator.md b/pages/common/verilator.md index cd7d6f260..bf78d0814 100644 --- a/pages/common/verilator.md +++ b/pages/common/verilator.md @@ -1,6 +1,6 @@ # verilator -> Converts Verilog and SystemVerilog hardware description language (HDL) designs into a C++ or SystemC model that after compiling can be executed. +> Converts Verilog and SystemVerilog hardware description language (HDL) design into a C++ or SystemC model to be executed after compiling. > More information: . - Build a specific C project in the current directory: