DawnMagnet/tldr
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

verilator: fix typo (#9559)

Browse Source
This commit is contained in:
K.B.Dharun Krishna
2022-11-29 00:06:58 +05:30
committed by GitHub
parent bf494772ba
commit 9272721e5a
1 changed files with 1 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
pages/common/verilator.md
View File

@@ -1,6 +1,6 @@
# verilator
> Converts Verilog and SystemVerilog hardware description language (HDL) designs into a C++ or SystemC model that after compiling can be executed.
> Converts Verilog and SystemVerilog hardware description language (HDL) design into a C++ or SystemC model to be executed after compiling.
> More information: <https://veripool.org/guide/latest/>.
- Build a specific C project in the current directory: